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74HC273D进口原装现货，欢迎来电咨询洽谈订购！  74HC273D.pdf
FEATURES
· Ideal buffer for MOS microprocessor or memory
· Common clock and master reset
· Eight positive edge-triggered D-type flip-flops
· See “377” for clock enable version
· See “373” for transparent latch version
· See “374” for 3-state version
· Output capability; standard
· ICC category: MSI GENERAL DESCRIPTION
The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements. 
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